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RTL Design Engineer

About the role

Own RTL blocks from microarchitecture through to clean synthesis. You will write the specification, implement the block, close lint and CDC, and support verification through to sign-off.

Responsibilities

Write microarchitecture specifications for assigned blocks. Implement RTL and close lint and CDC. Support verification on testbench requirements and coverage. Work with physical design on timing, area and power. Debug bring-up issues traced back to your blocks.

Skills

rtl design,verilog,systemverilog,uvm,synthesis,timing closure

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