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RTL Design Engineer

About the role

RTL Design Engineer - Permanent role in Hyderabad, responsible for designing and verifying digital circuits.

Responsibilities

Design RTL digital circuits Verify design using Verilog and SystemVerilog Create and manage UVM testbenches Perform synthesis and timing closure Collaborate with cross-functional teams Develop and maintain design documentation Participate in design reviews and feedback Ensure design meets project requirements Troubleshoot and debug design issues

Skills

rtl design,verilog,systemverilog,uvm,synthesis,timing closure

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