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RTL Design Engineer

About the role

Own RTL blocks for a production SoC from microarchitecture through to clean synthesis. You will write the specification, code the block, close lint, CDC and timing feedback with the physical design team, and support verification through to sign-off.

Responsibilities

Write microarchitecture specifications for assigned blocks. Implement RTL in SystemVerilog and close lint and CDC. Work with DV on testbench requirements and coverage closure. Support synthesis, timing and area targets with the PD team. Debug silicon bring-up issues traced back to your blocks.

Skills

Verilog, SystemVerilog, RTL design, Lint, CDC, synthesis, low power design, AMBA AXI/AHB

Preferred skills

UPF, lint, CDC and synthesis tooling, microarchitecture specification

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