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Design Verification Engineer (UVM)
- Reference: REQ-0103
- Location: Bengaluru
- Work mode: Hybrid
- Employment type: Permanent
- Experience: 3-7 years
- Department: Semiconductor Design
- Industry: Semiconductor / VLSI / Product Engineering
- Qualification: BE/BTech or ME/MTech in Electronics, Electrical or VLSI
- Positions: 4
- Posted: 2026-09-05
About the role
Verify SoC blocks and subsystems to coverage closure. You will build UVM environments, write the verification plan, drive constrained random and assertion-based verification, and sign off coverage before tape-out.
Responsibilities
Write the verification plan from the design specification. Build and extend UVM testbenches, sequences and scoreboards. Close functional and code coverage, and justify what is waived. Debug failures with the design owner rather than over the wall. Report readiness honestly against the tape-out schedule.
Skills
UVM, SystemVerilog, constrained random verification, functional coverage, assertions (SVA), testbench architecture
Preferred skills
Formal verification, industry-standard simulators, Python, AMBA protocol VIP, C/C++ reference models